[EDIT] FILE: cdsp_dtbs.elf
ELF ��4 4 � � �� ��� � � 8 8 CFGL � � �E � " default_process-hamoa-1.0-cdsp.dtb DF �E {� " default_process-purwa-1.0-cdsp.dtb � �� E� 8 =� ( � =t qcom,[soc] root-process-hamoa-1.0-cdsp soc , boot pinctrl@f100000 qcom,hamoa-pinctrl qcom,pinctrl 4 � 8 � ? E H P ` , qup0_se0_l0 l , ibi_i3c_qup0_se0_sda l , qup0_se0_l1 l , ibi_i3c_qup0_se0_scl l , qup0_se0_l2 l , qup0_se0_l3 l , qup0_se1_l0 l , qup0_se1_l1 l , qup0_se1_l2 l , qup0_se1_l3 l , qup0_se2_l0 l , qup0_se2_l1 l , qup0_se2_l2 l , qup0_se2_l3 l , qup0_se3_l0 l , qup0_se7_l2 l , qup0_se3_l1 l , qup0_se7_l3 l , qup0_se3_l2 l , qup0_se7_l0 l , qup0_se3_l3 l , qup0_se7_l1 l , qup0_se4_l0 l , qup0_se4_l1 l , qup0_se2_l4 l , qup0_se4_l2 l , qup0_se2_l5 l , qup0_se4_l3 l , qup0_se2_l6 l , qup0_se5_l0 l , qup0_se5_l1 l , ! qup0_se3_l6 l , " qup0_se5_l2 l , # qup0_se3_l5 l , $ qup0_se5_l3 l , % qup0_se3_l4 l , & qup0_se6_l0 l , ' qup0_se6_l1 l , ( qup0_se6_l2 l , ) qup0_se6_l3 l , * qup1_se0_l0 l , + ibi_i3c_qup1_se0_sda l , , qup1_se0_l1 l ! , - ibi_i3c_qup1_se0_scl l ! , . qup1_se3_l6 l ! , / qup1_se0_l2 l " , 0 qup1_se3_l5 l " , 1 qup1_se0_l3 l # , 2 qup1_se3_l4 l # , 3 qup1_se1_l0 l $ , 4 ibi_i3c_qup1_se1_sda l $ , 5 qup1_se1_l1 l % , 6 ibi_i3c_qup1_se1_scl l % , 7 qup1_se1_l2 l & , 8 qup1_se1_l3 l ' , 9 qup1_se2_l0 l ( , : qup1_se2_l1 l ) , ; qup1_se2_l2 l * , < qup1_se2_l3 l + , = qup1_se3_l0 l , , > qup1_se3_l1 l - , ? qup1_se3_l2 l . , @ qup1_se3_l3 l / , A qup1_se4_l0 l 0 , B qup1_se4_l1 l 1 , C qup1_se2_l4 l 1 , D qup1_se4_l2 l 2 , E qup1_se2_l5 l 2 , F qup1_se4_l3 l 3 , G qup1_se2_l6 l 3 , H qup1_se5_l0 l 4 , I qup1_se7_l2 l 4 , J qup1_se5_l1 l 5 , K qup1_se7_l3 l 5 , L qup1_se5_l2 l 6 , M qup1_se7_l0 l 6 , N qup1_se5_l3 l 7 , O qup1_se7_l1 l 7 , P qup1_se6_l0 l 8 , Q qup1_se6_l1 l 9 , R qup1_se6_l2 l : , S qup1_se6_l3 l ; , T qup2_se0_l0 l @ , U qup2_se0_l1 l A , V qup2_se3_l6 l A , W qup2_se0_l2 l B , X qup2_se3_l5 l B , Y qup2_se0_l3 l C , Z qup2_se3_l4 l C , [ qup2_se1_l0 l D , \ ibi_i3c_qup2_se1_sda l D , ] qup2_se1_l1 l E , ^ ibi_i3c_qup2_se1_scl l E , _ qup2_se1_l2 l F , ` qup2_se1_l3 l G , a qup2_se2_l0 l H , b qup2_se2_l1 l I , c qup2_se2_l2 l J , d qup2_se2_l3 l K , e qup2_se3_l0 l L , f qup2_se3_l1 l M , g qup2_se3_l2 l N , h qup2_se3_l3 l O , i qup2_se4_l0 l P , j qup2_se4_l1 l Q , k qup2_se2_l4 l Q , l qup2_se4_l2 l R , m qup2_se2_l5 l R , n qup2_se4_l3 l S , o qup2_se2_l6 l S , p qup2_se5_l0 l T , q qup2_se7_l2 l T , r qup2_se5_l1 l U , s qup2_se7_l3 l U , t qup2_se5_l2 l V , u qup2_se7_l0 l V , v qup2_se5_l3 l W , w qup2_se7_l1 l W , x qup2_se6_l0 l X , y qup2_se6_l1 l Y , z qup2_se6_l2 l Z , { qup2_se6_l3 l [ , | cci_i2c_sda0 l e , } cci_i2c_scl0 l f , ~ cci_i2c_sda1 l g , cci_i2c_scl1 l h , � cci_i2c_sda2 l i , � cci_i2c_scl2 l j , � qspi0_clk l , � qspi0_data_0 l � , � qspi0_data_1 l � , � qspi0_data_2 l � , � qspi0_data_3 l � , � qspi0_cs0_n l � , � qspi0_cs1_n l � , � aon_cci_i2c_sda3 l � , � aon_cci_i2c_scl3 l � , � sw , � core cpt_boot_test p ` | � test1 � � � � | � * �My Secret Message, Please keep it secret! test2 test_types � � � � � � � �� � �� �� �� �� ���������� test_pic_3 qcom,pic � test_uart1 qcom,uart � � base rx tx test_uart2 qcom,uart � PD_Access_control OEM_Flavor_Validation __symbols__ */soc ./soc/pinctrl@f100000 ! 3/soc/pinctrl@f100000/qup0_se0_l0 * ?/soc/pinctrl@f100000/ibi_i3c_qup0_se0_sda ! T/soc/pinctrl@f100000/qup0_se0_l1 * `/soc/pinctrl@f100000/ibi_i3c_qup0_se0_scl ! u/soc/pinctrl@f100000/qup0_se0_l2 ! �/soc/pinctrl@f100000/qup0_se0_l3 ! �/soc/pinctrl@f100000/qup0_se1_l0 ! �/soc/pinctrl@f100000/qup0_se1_l1 ! �/soc/pinctrl@f100000/qup0_se1_l2 ! �/soc/pinctrl@f100000/qup0_se1_l3 ! �/soc/pinctrl@f100000/qup0_se2_l0 ! �/soc/pinctrl@f100000/qup0_se2_l1 ! �/soc/pinctrl@f100000/qup0_se2_l2 ! �/soc/pinctrl@f100000/qup0_se2_l3 ! �/soc/pinctrl@f100000/qup0_se3_l0 ! �/soc/pinctrl@f100000/qup0_se7_l2 ! /soc/pinctrl@f100000/qup0_se3_l1 ! /soc/pinctrl@f100000/qup0_se7_l3 ! /soc/pinctrl@f100000/qup0_se3_l2 ! )/soc/pinctrl@f100000/qup0_se7_l0 ! 5/soc/pinctrl@f100000/qup0_se3_l3 ! A/soc/pinctrl@f100000/qup0_se7_l1 ! M/soc/pinctrl@f100000/qup0_se4_l0 ! Y/soc/pinctrl@f100000/qup0_se4_l1 ! e/soc/pinctrl@f100000/qup0_se2_l4 ! q/soc/pinctrl@f100000/qup0_se4_l2 ! }/soc/pinctrl@f100000/qup0_se2_l5 ! �/soc/pinctrl@f100000/qup0_se4_l3 ! �/soc/pinctrl@f100000/qup0_se2_l6 ! �/soc/pinctrl@f100000/qup0_se5_l0 ! �/soc/pinctrl@f100000/qup0_se5_l1 ! �/soc/pinctrl@f100000/qup0_se3_l6 ! �/soc/pinctrl@f100000/qup0_se5_l2 ! �/soc/pinctrl@f100000/qup0_se3_l5 ! �/soc/pinctrl@f100000/qup0_se5_l3 ! �/soc/pinctrl@f100000/qup0_se3_l4 ! �/soc/pinctrl@f100000/qup0_se6_l0 ! /soc/pinctrl@f100000/qup0_se6_l1 ! /soc/pinctrl@f100000/qup0_se6_l2 ! /soc/pinctrl@f100000/qup0_se6_l3 ! %/soc/pinctrl@f100000/qup1_se0_l0 * 1/soc/pinctrl@f100000/ibi_i3c_qup1_se0_sda ! F/soc/pinctrl@f100000/qup1_se0_l1 * R/soc/pinctrl@f100000/ibi_i3c_qup1_se0_scl ! g/soc/pinctrl@f100000/qup1_se3_l6 ! s/soc/pinctrl@f100000/qup1_se0_l2 ! /soc/pinctrl@f100000/qup1_se3_l5 ! �/soc/pinctrl@f100000/qup1_se0_l3 ! �/soc/pinctrl@f100000/qup1_se3_l4 ! �/soc/pinctrl@f100000/qup1_se1_l0 * �/soc/pinctrl@f100000/ibi_i3c_qup1_se1_sda ! �/soc/pinctrl@f100000/qup1_se1_l1 * �/soc/pinctrl@f100000/ibi_i3c_qup1_se1_scl ! �/soc/pinctrl@f100000/qup1_se1_l2 ! �/soc/pinctrl@f100000/qup1_se1_l3 ! �/soc/pinctrl@f100000/qup1_se2_l0 ! /soc/pinctrl@f100000/qup1_se2_l1 ! /soc/pinctrl@f100000/qup1_se2_l2 ! !/soc/pinctrl@f100000/qup1_se2_l3 ! -/soc/pinctrl@f100000/qup1_se3_l0 ! 9/soc/pinctrl@f100000/qup1_se3_l1 ! E/soc/pinctrl@f100000/qup1_se3_l2 ! Q/soc/pinctrl@f100000/qup1_se3_l3 ! ]/soc/pinctrl@f100000/qup1_se4_l0 ! i/soc/pinctrl@f100000/qup1_se4_l1 ! u/soc/pinctrl@f100000/qup1_se2_l4 ! �/soc/pinctrl@f100000/qup1_se4_l2 ! �/soc/pinctrl@f100000/qup1_se2_l5 ! �/soc/pinctrl@f100000/qup1_se4_l3 ! �/soc/pinctrl@f100000/qup1_se2_l6 ! �/soc/pinctrl@f100000/qup1_se5_l0 ! �/soc/pinctrl@f100000/qup1_se7_l2 ! �/soc/pinctrl@f100000/qup1_se5_l1 ! �/soc/pinctrl@f100000/qup1_se7_l3 ! �/soc/pinctrl@f100000/qup1_se5_l2 ! �/soc/pinctrl@f100000/qup1_se7_l0 ! �/soc/pinctrl@f100000/qup1_se5_l3 ! /soc/pinctrl@f100000/qup1_se7_l1 ! /soc/pinctrl@f100000/qup1_se6_l0 ! /soc/pinctrl@f100000/qup1_se6_l1 ! )/soc/pinctrl@f100000/qup1_se6_l2 ! 5/soc/pinctrl@f100000/qup1_se6_l3 ! A/soc/pinctrl@f100000/qup2_se0_l0 ! M/soc/pinctrl@f100000/qup2_se0_l1 ! Y/soc/pinctrl@f100000/qup2_se3_l6 ! e/soc/pinctrl@f100000/qup2_se0_l2 ! q/soc/pinctrl@f100000/qup2_se3_l5 ! }/soc/pinctrl@f100000/qup2_se0_l3 ! �/soc/pinctrl@f100000/qup2_se3_l4 ! �/soc/pinctrl@f100000/qup2_se1_l0 * �/soc/pinctrl@f100000/ibi_i3c_qup2_se1_sda ! �/soc/pinctrl@f100000/qup2_se1_l1 * �/soc/pinctrl@f100000/ibi_i3c_qup2_se1_scl ! �/soc/pinctrl@f100000/qup2_se1_l2 ! �/soc/pinctrl@f100000/qup2_se1_l3 ! �/soc/pinctrl@f100000/qup2_se2_l0 ! �/soc/pinctrl@f100000/qup2_se2_l1 ! /soc/pinctrl@f100000/qup2_se2_l2 ! /soc/pinctrl@f100000/qup2_se2_l3 ! /soc/pinctrl@f100000/qup2_se3_l0 ! +/soc/pinctrl@f100000/qup2_se3_l1 ! 7/soc/pinctrl@f100000/qup2_se3_l2 ! C/soc/pinctrl@f100000/qup2_se3_l3 ! O/soc/pinctrl@f100000/qup2_se4_l0 ! [/soc/pinctrl@f100000/qup2_se4_l1 ! g/soc/pinctrl@f100000/qup2_se2_l4 ! s/soc/pinctrl@f100000/qup2_se4_l2 ! /soc/pinctrl@f100000/qup2_se2_l5 ! �/soc/pinctrl@f100000/qup2_se4_l3 ! �/soc/pinctrl@f100000/qup2_se2_l6 ! �/soc/pinctrl@f100000/qup2_se5_l0 ! �/soc/pinctrl@f100000/qup2_se7_l2 ! �/soc/pinctrl@f100000/qup2_se5_l1 ! �/soc/pinctrl@f100000/qup2_se7_l3 ! �/soc/pinctrl@f100000/qup2_se5_l2 ! �/soc/pinctrl@f100000/qup2_se7_l0 ! �/soc/pinctrl@f100000/qup2_se5_l3 ! �/soc/pinctrl@f100000/qup2_se7_l1 ! /soc/pinctrl@f100000/qup2_se6_l0 ! /soc/pinctrl@f100000/qup2_se6_l1 ! /soc/pinctrl@f100000/qup2_se6_l2 ! '/soc/pinctrl@f100000/qup2_se6_l3 " 3/soc/pinctrl@f100000/cci_i2c_sda0 " @/soc/pinctrl@f100000/cci_i2c_scl0 " M/soc/pinctrl@f100000/cci_i2c_sda1 " Z/soc/pinctrl@f100000/cci_i2c_scl1 " g/soc/pinctrl@f100000/cci_i2c_sda2 " t/soc/pinctrl@f100000/cci_i2c_scl2 �/soc/pinctrl@f100000/qspi0_clk " �/soc/pinctrl@f100000/qspi0_data_0 " �/soc/pinctrl@f100000/qspi0_data_1 " �/soc/pinctrl@f100000/qspi0_data_2 " �/soc/pinctrl@f100000/qspi0_data_3 ! �/soc/pinctrl@f100000/qspi0_cs0_n ! �/soc/pinctrl@f100000/qspi0_cs1_n & �/soc/pinctrl@f100000/aon_cci_i2c_sda3 & �/soc/pinctrl@f100000/aon_cci_i2c_scl3 �/sw model compatible #address-cells #size-cells phandle reg ngpios width id version gpio-controller #gpio-cells mux test_config test_bool1 test_bool2 test_ver test_uint8_list test_uint32 test_uint32_list test_string test_uint8 test_uint16 test_uint16_list reg_alt reg-names PD_indicator test_oem_entry soc tlmm qup0_se0_l0 ibi_i3c_qup0_se0_sda qup0_se0_l1 ibi_i3c_qup0_se0_scl qup0_se0_l2 qup0_se0_l3 qup0_se1_l0 qup0_se1_l1 qup0_se1_l2 qup0_se1_l3 qup0_se2_l0 qup0_se2_l1 qup0_se2_l2 qup0_se2_l3 qup0_se3_l0 qup0_se7_l2 qup0_se3_l1 qup0_se7_l3 qup0_se3_l2 qup0_se7_l0 qup0_se3_l3 qup0_se7_l1 qup0_se4_l0 qup0_se4_l1 qup0_se2_l4 qup0_se4_l2 qup0_se2_l5 qup0_se4_l3 qup0_se2_l6 qup0_se5_l0 qup0_se5_l1 qup0_se3_l6 qup0_se5_l2 qup0_se3_l5 qup0_se5_l3 qup0_se3_l4 qup0_se6_l0 qup0_se6_l1 qup0_se6_l2 qup0_se6_l3 qup1_se0_l0 ibi_i3c_qup1_se0_sda qup1_se0_l1 ibi_i3c_qup1_se0_scl qup1_se3_l6 qup1_se0_l2 qup1_se3_l5 qup1_se0_l3 qup1_se3_l4 qup1_se1_l0 ibi_i3c_qup1_se1_sda qup1_se1_l1 ibi_i3c_qup1_se1_scl qup1_se1_l2 qup1_se1_l3 qup1_se2_l0 qup1_se2_l1 qup1_se2_l2 qup1_se2_l3 qup1_se3_l0 qup1_se3_l1 qup1_se3_l2 qup1_se3_l3 qup1_se4_l0 qup1_se4_l1 qup1_se2_l4 qup1_se4_l2 qup1_se2_l5 qup1_se4_l3 qup1_se2_l6 qup1_se5_l0 qup1_se7_l2 qup1_se5_l1 qup1_se7_l3 qup1_se5_l2 qup1_se7_l0 qup1_se5_l3 qup1_se7_l1 qup1_se6_l0 qup1_se6_l1 qup1_se6_l2 qup1_se6_l3 qup2_se0_l0 qup2_se0_l1 qup2_se3_l6 qup2_se0_l2 qup2_se3_l5 qup2_se0_l3 qup2_se3_l4 qup2_se1_l0 ibi_i3c_qup2_se1_sda qup2_se1_l1 ibi_i3c_qup2_se1_scl qup2_se1_l2 qup2_se1_l3 qup2_se2_l0 qup2_se2_l1 qup2_se2_l2 qup2_se2_l3 qup2_se3_l0 qup2_se3_l1 qup2_se3_l2 qup2_se3_l3 qup2_se4_l0 qup2_se4_l1 qup2_se2_l4 qup2_se4_l2 qup2_se2_l5 qup2_se4_l3 qup2_se2_l6 qup2_se5_l0 qup2_se7_l2 qup2_se5_l1 qup2_se7_l3 qup2_se5_l2 qup2_se7_l0 qup2_se5_l3 qup2_se7_l1 qup2_se6_l0 qup2_se6_l1 qup2_se6_l2 qup2_se6_l3 cci_i2c_sda0 cci_i2c_scl0 cci_i2c_sda1 cci_i2c_scl1 cci_i2c_sda2 cci_i2c_scl2 qspi0_clk qspi0_data_0 qspi0_data_1 qspi0_data_2 qspi0_data_3 qspi0_cs0_n qspi0_cs1_n aon_cci_i2c_sda3 aon_cci_i2c_scl3 sw � �� E� 8 =� ( � =t qcom,purwa root-process-purwa-1.0-cdsp soc , pinctrl@f100000 qcom,hamoa-pinctrl qcom,pinctrl 4 � 8 � ? E H P ` , qup0_se0_l0 l , ibi_i3c_qup0_se0_sda l , qup0_se0_l1 l , ibi_i3c_qup0_se0_scl l , qup0_se0_l2 l , qup0_se0_l3 l , qup0_se1_l0 l , qup0_se1_l1 l , qup0_se1_l2 l , qup0_se1_l3 l , qup0_se2_l0 l , qup0_se2_l1 l , qup0_se2_l2 l , qup0_se2_l3 l , qup0_se3_l0 l , qup0_se7_l2 l , qup0_se3_l1 l , qup0_se7_l3 l , qup0_se3_l2 l , qup0_se7_l0 l , qup0_se3_l3 l , qup0_se7_l1 l , qup0_se4_l0 l , qup0_se4_l1 l , qup0_se2_l4 l , qup0_se4_l2 l , qup0_se2_l5 l , qup0_se4_l3 l , qup0_se2_l6 l , qup0_se5_l0 l , qup0_se5_l1 l , ! qup0_se3_l6 l , " qup0_se5_l2 l , # qup0_se3_l5 l , $ qup0_se5_l3 l , % qup0_se3_l4 l , & qup0_se6_l0 l , ' qup0_se6_l1 l , ( qup0_se6_l2 l , ) qup0_se6_l3 l , * qup1_se0_l0 l , + ibi_i3c_qup1_se0_sda l , , qup1_se0_l1 l ! , - ibi_i3c_qup1_se0_scl l ! , . qup1_se3_l6 l ! , / qup1_se0_l2 l " , 0 qup1_se3_l5 l " , 1 qup1_se0_l3 l # , 2 qup1_se3_l4 l # , 3 qup1_se1_l0 l $ , 4 ibi_i3c_qup1_se1_sda l $ , 5 qup1_se1_l1 l % , 6 ibi_i3c_qup1_se1_scl l % , 7 qup1_se1_l2 l & , 8 qup1_se1_l3 l ' , 9 qup1_se2_l0 l ( , : qup1_se2_l1 l ) , ; qup1_se2_l2 l * , < qup1_se2_l3 l + , = qup1_se3_l0 l , , > qup1_se3_l1 l - , ? qup1_se3_l2 l . , @ qup1_se3_l3 l / , A qup1_se4_l0 l 0 , B qup1_se4_l1 l 1 , C qup1_se2_l4 l 1 , D qup1_se4_l2 l 2 , E qup1_se2_l5 l 2 , F qup1_se4_l3 l 3 , G qup1_se2_l6 l 3 , H qup1_se5_l0 l 4 , I qup1_se7_l2 l 4 , J qup1_se5_l1 l 5 , K qup1_se7_l3 l 5 , L qup1_se5_l2 l 6 , M qup1_se7_l0 l 6 , N qup1_se5_l3 l 7 , O qup1_se7_l1 l 7 , P qup1_se6_l0 l 8 , Q qup1_se6_l1 l 9 , R qup1_se6_l2 l : , S qup1_se6_l3 l ; , T qup2_se0_l0 l @ , U qup2_se0_l1 l A , V qup2_se3_l6 l A , W qup2_se0_l2 l B , X qup2_se3_l5 l B , Y qup2_se0_l3 l C , Z qup2_se3_l4 l C , [ qup2_se1_l0 l D , \ ibi_i3c_qup2_se1_sda l D , ] qup2_se1_l1 l E , ^ ibi_i3c_qup2_se1_scl l E , _ qup2_se1_l2 l F , ` qup2_se1_l3 l G , a qup2_se2_l0 l H , b qup2_se2_l1 l I , c qup2_se2_l2 l J , d qup2_se2_l3 l K , e qup2_se3_l0 l L , f qup2_se3_l1 l M , g qup2_se3_l2 l N , h qup2_se3_l3 l O , i qup2_se4_l0 l P , j qup2_se4_l1 l Q , k qup2_se2_l4 l Q , l qup2_se4_l2 l R , m qup2_se2_l5 l R , n qup2_se4_l3 l S , o qup2_se2_l6 l S , p qup2_se5_l0 l T , q qup2_se7_l2 l T , r qup2_se5_l1 l U , s qup2_se7_l3 l U , t qup2_se5_l2 l V , u qup2_se7_l0 l V , v qup2_se5_l3 l W , w qup2_se7_l1 l W , x qup2_se6_l0 l X , y qup2_se6_l1 l Y , z qup2_se6_l2 l Z , { qup2_se6_l3 l [ , | cci_i2c_sda0 l e , } cci_i2c_scl0 l f , ~ cci_i2c_sda1 l g , cci_i2c_scl1 l h , � cci_i2c_sda2 l i , � cci_i2c_scl2 l j , � qspi0_clk l , � qspi0_data_0 l � , � qspi0_data_1 l � , � qspi0_data_2 l � , � qspi0_data_3 l � , � qspi0_cs0_n l � , � qspi0_cs1_n l � , � aon_cci_i2c_sda3 l � , � aon_cci_i2c_scl3 l � , � boot sw , � core cpt_boot_test p ` | � test1 � � � � | � * �My Secret Message, Please keep it secret! test2 test_types � � � � � � � �� � �� �� �� �� ���������� test_pic_3 qcom,pic � test_uart1 qcom,uart � � base rx tx test_uart2 qcom,uart � PD_Access_control OEM_Flavor_Validation __symbols__ */soc ./soc/pinctrl@f100000 ! 3/soc/pinctrl@f100000/qup0_se0_l0 * ?/soc/pinctrl@f100000/ibi_i3c_qup0_se0_sda ! T/soc/pinctrl@f100000/qup0_se0_l1 * `/soc/pinctrl@f100000/ibi_i3c_qup0_se0_scl ! u/soc/pinctrl@f100000/qup0_se0_l2 ! �/soc/pinctrl@f100000/qup0_se0_l3 ! �/soc/pinctrl@f100000/qup0_se1_l0 ! �/soc/pinctrl@f100000/qup0_se1_l1 ! �/soc/pinctrl@f100000/qup0_se1_l2 ! �/soc/pinctrl@f100000/qup0_se1_l3 ! �/soc/pinctrl@f100000/qup0_se2_l0 ! �/soc/pinctrl@f100000/qup0_se2_l1 ! �/soc/pinctrl@f100000/qup0_se2_l2 ! �/soc/pinctrl@f100000/qup0_se2_l3 ! �/soc/pinctrl@f100000/qup0_se3_l0 ! �/soc/pinctrl@f100000/qup0_se7_l2 ! /soc/pinctrl@f100000/qup0_se3_l1 ! /soc/pinctrl@f100000/qup0_se7_l3 ! /soc/pinctrl@f100000/qup0_se3_l2 ! )/soc/pinctrl@f100000/qup0_se7_l0 ! 5/soc/pinctrl@f100000/qup0_se3_l3 ! A/soc/pinctrl@f100000/qup0_se7_l1 ! M/soc/pinctrl@f100000/qup0_se4_l0 ! Y/soc/pinctrl@f100000/qup0_se4_l1 ! e/soc/pinctrl@f100000/qup0_se2_l4 ! q/soc/pinctrl@f100000/qup0_se4_l2 ! }/soc/pinctrl@f100000/qup0_se2_l5 ! �/soc/pinctrl@f100000/qup0_se4_l3 ! �/soc/pinctrl@f100000/qup0_se2_l6 ! �/soc/pinctrl@f100000/qup0_se5_l0 ! �/soc/pinctrl@f100000/qup0_se5_l1 ! �/soc/pinctrl@f100000/qup0_se3_l6 ! �/soc/pinctrl@f100000/qup0_se5_l2 ! �/soc/pinctrl@f100000/qup0_se3_l5 ! �/soc/pinctrl@f100000/qup0_se5_l3 ! �/soc/pinctrl@f100000/qup0_se3_l4 ! �/soc/pinctrl@f100000/qup0_se6_l0 ! /soc/pinctrl@f100000/qup0_se6_l1 ! /soc/pinctrl@f100000/qup0_se6_l2 ! /soc/pinctrl@f100000/qup0_se6_l3 ! %/soc/pinctrl@f100000/qup1_se0_l0 * 1/soc/pinctrl@f100000/ibi_i3c_qup1_se0_sda ! F/soc/pinctrl@f100000/qup1_se0_l1 * R/soc/pinctrl@f100000/ibi_i3c_qup1_se0_scl ! g/soc/pinctrl@f100000/qup1_se3_l6 ! s/soc/pinctrl@f100000/qup1_se0_l2 ! /soc/pinctrl@f100000/qup1_se3_l5 ! �/soc/pinctrl@f100000/qup1_se0_l3 ! �/soc/pinctrl@f100000/qup1_se3_l4 ! �/soc/pinctrl@f100000/qup1_se1_l0 * �/soc/pinctrl@f100000/ibi_i3c_qup1_se1_sda ! �/soc/pinctrl@f100000/qup1_se1_l1 * �/soc/pinctrl@f100000/ibi_i3c_qup1_se1_scl ! �/soc/pinctrl@f100000/qup1_se1_l2 ! �/soc/pinctrl@f100000/qup1_se1_l3 ! �/soc/pinctrl@f100000/qup1_se2_l0 ! /soc/pinctrl@f100000/qup1_se2_l1 ! /soc/pinctrl@f100000/qup1_se2_l2 ! !/soc/pinctrl@f100000/qup1_se2_l3 ! -/soc/pinctrl@f100000/qup1_se3_l0 ! 9/soc/pinctrl@f100000/qup1_se3_l1 ! E/soc/pinctrl@f100000/qup1_se3_l2 ! Q/soc/pinctrl@f100000/qup1_se3_l3 ! ]/soc/pinctrl@f100000/qup1_se4_l0 ! i/soc/pinctrl@f100000/qup1_se4_l1 ! u/soc/pinctrl@f100000/qup1_se2_l4 ! �/soc/pinctrl@f100000/qup1_se4_l2 ! �/soc/pinctrl@f100000/qup1_se2_l5 ! �/soc/pinctrl@f100000/qup1_se4_l3 ! �/soc/pinctrl@f100000/qup1_se2_l6 ! �/soc/pinctrl@f100000/qup1_se5_l0 ! �/soc/pinctrl@f100000/qup1_se7_l2 ! �/soc/pinctrl@f100000/qup1_se5_l1 ! �/soc/pinctrl@f100000/qup1_se7_l3 ! �/soc/pinctrl@f100000/qup1_se5_l2 ! �/soc/pinctrl@f100000/qup1_se7_l0 ! �/soc/pinctrl@f100000/qup1_se5_l3 ! /soc/pinctrl@f100000/qup1_se7_l1 ! /soc/pinctrl@f100000/qup1_se6_l0 ! /soc/pinctrl@f100000/qup1_se6_l1 ! )/soc/pinctrl@f100000/qup1_se6_l2 ! 5/soc/pinctrl@f100000/qup1_se6_l3 ! A/soc/pinctrl@f100000/qup2_se0_l0 ! M/soc/pinctrl@f100000/qup2_se0_l1 ! Y/soc/pinctrl@f100000/qup2_se3_l6 ! e/soc/pinctrl@f100000/qup2_se0_l2 ! q/soc/pinctrl@f100000/qup2_se3_l5 ! }/soc/pinctrl@f100000/qup2_se0_l3 ! �/soc/pinctrl@f100000/qup2_se3_l4 ! �/soc/pinctrl@f100000/qup2_se1_l0 * �/soc/pinctrl@f100000/ibi_i3c_qup2_se1_sda ! �/soc/pinctrl@f100000/qup2_se1_l1 * �/soc/pinctrl@f100000/ibi_i3c_qup2_se1_scl ! �/soc/pinctrl@f100000/qup2_se1_l2 ! �/soc/pinctrl@f100000/qup2_se1_l3 ! �/soc/pinctrl@f100000/qup2_se2_l0 ! �/soc/pinctrl@f100000/qup2_se2_l1 ! /soc/pinctrl@f100000/qup2_se2_l2 ! /soc/pinctrl@f100000/qup2_se2_l3 ! /soc/pinctrl@f100000/qup2_se3_l0 ! +/soc/pinctrl@f100000/qup2_se3_l1 ! 7/soc/pinctrl@f100000/qup2_se3_l2 ! C/soc/pinctrl@f100000/qup2_se3_l3 ! O/soc/pinctrl@f100000/qup2_se4_l0 ! [/soc/pinctrl@f100000/qup2_se4_l1 ! g/soc/pinctrl@f100000/qup2_se2_l4 ! s/soc/pinctrl@f100000/qup2_se4_l2 ! /soc/pinctrl@f100000/qup2_se2_l5 ! �/soc/pinctrl@f100000/qup2_se4_l3 ! �/soc/pinctrl@f100000/qup2_se2_l6 ! �/soc/pinctrl@f100000/qup2_se5_l0 ! �/soc/pinctrl@f100000/qup2_se7_l2 ! �/soc/pinctrl@f100000/qup2_se5_l1 ! �/soc/pinctrl@f100000/qup2_se7_l3 ! �/soc/pinctrl@f100000/qup2_se5_l2 ! �/soc/pinctrl@f100000/qup2_se7_l0 ! �/soc/pinctrl@f100000/qup2_se5_l3 ! �/soc/pinctrl@f100000/qup2_se7_l1 ! /soc/pinctrl@f100000/qup2_se6_l0 ! /soc/pinctrl@f100000/qup2_se6_l1 ! /soc/pinctrl@f100000/qup2_se6_l2 ! '/soc/pinctrl@f100000/qup2_se6_l3 " 3/soc/pinctrl@f100000/cci_i2c_sda0 " @/soc/pinctrl@f100000/cci_i2c_scl0 " M/soc/pinctrl@f100000/cci_i2c_sda1 " Z/soc/pinctrl@f100000/cci_i2c_scl1 " g/soc/pinctrl@f100000/cci_i2c_sda2 " t/soc/pinctrl@f100000/cci_i2c_scl2 �/soc/pinctrl@f100000/qspi0_clk " �/soc/pinctrl@f100000/qspi0_data_0 " �/soc/pinctrl@f100000/qspi0_data_1 " �/soc/pinctrl@f100000/qspi0_data_2 " �/soc/pinctrl@f100000/qspi0_data_3 ! �/soc/pinctrl@f100000/qspi0_cs0_n ! �/soc/pinctrl@f100000/qspi0_cs1_n & �/soc/pinctrl@f100000/aon_cci_i2c_sda3 & �/soc/pinctrl@f100000/aon_cci_i2c_scl3 �/sw model compatible #address-cells #size-cells phandle reg ngpios width id version gpio-controller #gpio-cells mux test_config test_bool1 test_bool2 test_ver test_uint8_list test_uint32 test_uint32_list test_string test_uint8 test_uint16 test_uint16_list reg_alt reg-names PD_indicator test_oem_entry soc tlmm qup0_se0_l0 ibi_i3c_qup0_se0_sda qup0_se0_l1 ibi_i3c_qup0_se0_scl qup0_se0_l2 qup0_se0_l3 qup0_se1_l0 qup0_se1_l1 qup0_se1_l2 qup0_se1_l3 qup0_se2_l0 qup0_se2_l1 qup0_se2_l2 qup0_se2_l3 qup0_se3_l0 qup0_se7_l2 qup0_se3_l1 qup0_se7_l3 qup0_se3_l2 qup0_se7_l0 qup0_se3_l3 qup0_se7_l1 qup0_se4_l0 qup0_se4_l1 qup0_se2_l4 qup0_se4_l2 qup0_se2_l5 qup0_se4_l3 qup0_se2_l6 qup0_se5_l0 qup0_se5_l1 qup0_se3_l6 qup0_se5_l2 qup0_se3_l5 qup0_se5_l3 qup0_se3_l4 qup0_se6_l0 qup0_se6_l1 qup0_se6_l2 qup0_se6_l3 qup1_se0_l0 ibi_i3c_qup1_se0_sda qup1_se0_l1 ibi_i3c_qup1_se0_scl qup1_se3_l6 qup1_se0_l2 qup1_se3_l5 qup1_se0_l3 qup1_se3_l4 qup1_se1_l0 ibi_i3c_qup1_se1_sda qup1_se1_l1 ibi_i3c_qup1_se1_scl qup1_se1_l2 qup1_se1_l3 qup1_se2_l0 qup1_se2_l1 qup1_se2_l2 qup1_se2_l3 qup1_se3_l0 qup1_se3_l1 qup1_se3_l2 qup1_se3_l3 qup1_se4_l0 qup1_se4_l1 qup1_se2_l4 qup1_se4_l2 qup1_se2_l5 qup1_se4_l3 qup1_se2_l6 qup1_se5_l0 qup1_se7_l2 qup1_se5_l1 qup1_se7_l3 qup1_se5_l2 qup1_se7_l0 qup1_se5_l3 qup1_se7_l1 qup1_se6_l0 qup1_se6_l1 qup1_se6_l2 qup1_se6_l3 qup2_se0_l0 qup2_se0_l1 qup2_se3_l6 qup2_se0_l2 qup2_se3_l5 qup2_se0_l3 qup2_se3_l4 qup2_se1_l0 ibi_i3c_qup2_se1_sda qup2_se1_l1 ibi_i3c_qup2_se1_scl qup2_se1_l2 qup2_se1_l3 qup2_se2_l0 qup2_se2_l1 qup2_se2_l2 qup2_se2_l3 qup2_se3_l0 qup2_se3_l1 qup2_se3_l2 qup2_se3_l3 qup2_se4_l0 qup2_se4_l1 qup2_se2_l4 qup2_se4_l2 qup2_se2_l5 qup2_se4_l3 qup2_se2_l6 qup2_se5_l0 qup2_se7_l2 qup2_se5_l1 qup2_se7_l3 qup2_se5_l2 qup2_se7_l0 qup2_se5_l3 qup2_se7_l1 qup2_se6_l0 qup2_se6_l1 qup2_se6_l2 qup2_se6_l3 cci_i2c_sda0 cci_i2c_scl0 cci_i2c_sda1 cci_i2c_scl1 cci_i2c_sda2 cci_i2c_scl2 qspi0_clk qspi0_data_0 qspi0_data_1 qspi0_data_2 qspi0_data_3 qspi0_cs0_n qspi0_cs1_n aon_cci_i2c_sda3 aon_cci_i2c_scl3 sw � � h R � � M VV 0���v� SAh�K�'�ʗ}��8} ��֫��ć+ &�Ҏْ��H�i7Նi�+d�e*Y���֎ٌ�� ,��=��P1��M��J �ҦM���I �� 0e1 ���~��K�WG>�J7�I.������KZf` �i ���f$�e}�05��qCm�DL�D J��K�ph)8�$F�հV��Y 0[���t�� 0�g0��K��*4j�dfe �6y�40 *�H�=0~1$0"U Qualcomm Technologies, Inc.1*0(U !Qualcomm Cryptographic Operations1*0(U !QMC Attestation Root CA 6 SubCA 10 250603154704Z 270603154704Z0W1 0 UUS1 0 UCA10U San Diego10U QUALCOMM10U CASS - SBL40v0*�H�=+� "b P�+ lY���fɢ �H�7��� �������m<��� |_5�R ��\ lU�O2��J�SX-p<�0b�x������%��w��Sr�Z` � �|l3;��S0Q0 U #0��=p�Y��M�(M�R���}�0 U 0 0U ��0U % 0 +0 *�H�=h 0e1 ��w���/�ԉ��J �Ύ�����^�'~ �1�/9D��ɻ:�Z�0pΒx��w�~������}i�s)��=>R�Nyà�� C�V3�i ��0��0� �a�-��Ch��+���9G0 *�H�=0v1$0"U Qualcomm Technologies, Inc.1*0(U !Qualcomm Cryptographic Operations1"0 U QMC Attestation Root CA 60 200825214632Z 300825214632Z0~1$0"U Qualcomm Technologies, Inc.1*0(U !Qualcomm Cryptographic Operations1*0(U !QMC Attestation Root CA 6 SubCA 10v0*�H�=+� "b � �� �5�K�B�bˢ§H}��g�?#��N�;���FĬ���3�Z��3�;([��ݳ_�| ��9�| k�C��{#�R| H&"7?�@����f0d0U �0� 0U �0 U �=p�Y��M�(M�R���}�0 U #0��� �a���P���Ah�40 *�H�=i 0f1 � ��� ���ά�G� �O &����}��ef `��n�ӻR I�(�A�M1 ��\y�0���lx����������oV ���S#� ^S��-u6�T0�d0�� ��:=�H\�0 *�H�=0v1$0"U Qualcomm Technologies, Inc.1*0(U !Qualcomm Cryptographic Operations1"0 U QMC Attestation Root CA 60 200825214234Z20500825214234Z0v1$0"U Qualcomm Technologies, Inc.1*0(U !Qualcomm Cryptographic Operations1"0 U QMC Attestation Root CA 60v0*�H�=+� "b K̏L�!��W&4�ZP�?6@ >� n��t8 �TF!�_¤W[F�˝�� �5җ�FV��^�6\p�p�����N��h���A�E z5����B0@0U �0�0U �0 U �� �a���P���Ah�40 *�H�=h 0e1 ��S )܇DA,N�R�E\��Z��w���w�:��:�Z@��� |_0w�Q� ,ۂԅXE�@�Ə�C�'�;���A�xNg�n��T�"�Ґ �2����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������
SAVE
CANCEL